The present invention relates to single in-line memory modules (SIMMs) and dual in-line modules (DIMMs), and more particularly to the routing of traces on such modules.
SIMM and DIMM modules have gained enormous popularity, with most personal computers being shipped with sockets for such modules. This enables a user to later add additional modules increasing the memory capacity. There are also cache SRAM modules and the INTEL Klamath CPU (Pentium II) module with on-board SRAM.
Memory modules are made in many different sizes and capabilities, with the older 30-pin modules being replaced with 72-pin and 168-pin modules. The "pins" were original pins extending from the module's edge, but now most modules are leadless, having metal contact pads or leads. The modules contain a small printed-circuit board substrate, typically a multi-layer board with alternating laminated layers of fiberglass insulation and foil or metal interconnect layers. Surface mounted components are soldered onto one or both surfaces of the substrate.
The cache SRAM used in the Pentium motherboard is a level II cache. The planned Intel Klamath is meant to be the successor of the well-known Pentium Pro. The Klamath doesn't include any 2nd level cach, as its predecessor the Pentium Pro does. Instead, the 2nd level cache (256K or 512K) will be external to the Klamath and integrated onto a module (or slot card) with the Klamath processor. The 256K cache would be typically configured as 32K.times.64 bits, while the 512K cache would be configured as 64K.times.64 bits.
The older 30-pin modules typically had 8 data input/output (I/O) pins or leads. The new 168-pin modules have 64 data I/Os. In some configurations, the data I/Os are shared among multiple memory chips.
Increased numbers of pins and sizes of the memory chips has increased the difficulties of laying out the traces to connect to the memory module connector. Large numbers of "cross-unders" (alternately called "cross-overs") are required, wherein a trace is connected by a via to a second layer in the substrate so that it can cross under a trace which is in its way. For the new 168-pin module and 16 Meg SDRAM, manufacturers are producing a 6-layer circuit board substrate in order to accommodate the trace layout complexities. This significantly increases the cost of the memory module, offsetting the price advantage of the higher density DRAM. In addition, the large number of traces and the distances required affect timing and noise, and in particular can cause problems for timing-sensitive synchronous DRAMs (SDRAM).
The JEDEC standard for the memory modules attempts to address the optimum layout for assigning pins or contacts. For the 168-pin module, half of the data inputs are roughly grouped on the left side of the module, while the other half are grouped on the right side. In addition, chip designs take into consideration layout issues. For example, a 4 data bit chip will have bits D0 and D1 from top to bottom on the left side of the chip, while the right side will start with D3 at the top and have D2 at the bottom, thus enabling connecting via traces to four sequential data pins without requiring any cross-unders for that chip. However, as the number of data inputs per chip increases, and especially where multiple chips share these same data lines, cross-overs cannot be avoided.